김주호 연구실

Contemporary telecommunication device and computer are made by VLSI chip design. CAD & VLSI research is related to chip design environment development with broad application areas.

Research on optimized designs for high performance and low power consumption including Gate Sizing Method, Glitch Reduction, and Buffer Insertion techniques.

Statistical timing analysis for probabilistic modeling and calculation to handle process variations in semiconductor manufacturing, addressing limitations of traditional corner-based analysis.

Timing analysis for three-dimensional integrated circuits with multiple stacked layers connected by through-silicon vias (TSVs) and microbumps, considering timing constraints across layers.

Impact of physical circuit layout on performance including transistor, wire, and via effects on signal timing and delay variations, requiring advanced parasitic extraction and interconnect modeling.