김주호 연구실

Contemporary telecommunication device and computer are made by VLSI chip design. CAD & VLSI research is related to chip design environment development with broad application areas.

Research on optimized designs for high performance and low power consumption including Gate Sizing Method, Glitch Reduction, and Buffer Insertion techniques.

Statistical timing analysis methodology that considers process variations and probabilistic modeling for semiconductor performance analysis, addressing limitations of traditional corner-based approaches.

Timing analysis for three-dimensional integrated circuits with multiple stacked layers connected by through-silicon vias (TSVs) and microbumps, considering timing constraints across layers.

Impact of physical circuit layout on performance, including effects of transistors, wires, and vias on signal timing and delay variations, with optimization techniques for timing performance.